Cyient Semiconductors Non-public Restricted, a fast-growing customized silicon firm based mostly in Hyderabad, and MIPS, a world chief in RISC-V processor IP, immediately introduced a strategic collaboration to develop domain-optimized ASIC (application-specific built-in circuit) and ASSP (application-specific normal product) options that leverage the MIPS Atlas portfolio of superior, environment friendly processor IP.
Picture Credit score: Cyient Semiconductors Non-public Restricted
The partnership will give attention to enabling real-time, safety-critical purposes, energy supply, and compute effectivity in demanding platforms for automotive, industrial, and knowledge middle markets. Motor Management & Knowledge Middle Energy Supply are focal platforms to leverage Cyient’s Analog Combined Sign capabilities and MIPS Atlas CPU IP.
“As compute methods scale from cloud to the sting, clever energy supply is rising as a key enabler of efficiency and effectivity,” mentioned Suman Narayan, CEO of Cyient Semiconductors. “Our collaboration with MIPS permits us to carry collectively embedded intelligence and superior energy architectures in customized silicon platforms constructed on a scalable, open basis. Collectively, we’re designing tomorrow’s semiconductors — purpose-built for a extra related and power-efficient world.”
“The issue of energy effectivity and motor management are each real-time compute workloads for which MIPS M8500 microcontrollers are the optimum alternative,” mentioned Sameer Wasson, CEO of MIPS. “Constructing round our best-in-class real-time and control-loop efficiency and effectivity, Cyient can carry their distinctive functionality in clever energy supply into customized ASIC and ASSP designs to construct differentiated options that meet our clients distinctive wants of their goal markets.”
Demand for software program outlined automobiles, knowledge middle infrastructure, and industrial automation is driving progress for customized silicon. Clients can construct superior, differentiated options
which can be simple to program utilizing MIPS superior processor IP, based mostly on the open RISC-V instruction set structure, mixed with Cyient clever energy and mixed-signal design experience.
Focused purposes embody motor drive management, clever energy administration, energy supply administration, and safety-critical purposes, supplied as ASSP or ASIC platforms. OEMs and system integrators will profit from quicker time-to-market, avoiding proprietary lock-ins, and optimized platform price.
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