To deal with this hole and assist the ecosystem with deploying sturdy defenses, Google has supported educational analysis and developed check platforms to research DDR5 reminiscence. Our effort has led to the invention of recent assaults and a deeper understanding of Rowhammer on the present DRAM modules, serving to to forge the best way for additional, stronger mitigations.
What’s Rowhammer?
Rowhammer exploits a vulnerability in DRAM. DRAM cells retailer information as electrical costs, however these electrical costs leak over time, inflicting information corruption. To stop information loss, the reminiscence controller periodically refreshes the cells. Nonetheless, if a cell discharges earlier than the refresh cycle, its saved bit could corrupt. Initially thought-about a reliability problem, it has been leveraged by safety researchers to show privilege escalation assaults. By repeatedly accessing a reminiscence row, an attacker could cause bit flips in neighboring rows. An adversary can exploit Rowhammer through:
Reliably trigger bit flips by repeatedly accessing adjoining DRAM rows.
Coerce different purposes or the OS into utilizing these susceptible reminiscence pages.
Goal security-sensitive code or information to realize privilege escalation.
Or just corrupt system’s reminiscence to trigger denial of service.
Earlier work has repeatedly demonstrated the potential of such assaults from software program (Revisiting rowhammer, Are we prone to rowhammer?, Drammer, Flip feng shui, Jolt). Because of this, defending towards Rowhammer is required for safe isolation in multi-tenant environments just like the cloud.
Rowhammer Mitigations
The first strategy to mitigate Rowhammer is to detect which reminiscence rows are being aggressively accessed and refreshing close by rows earlier than a bit flip happens. TRR is a typical instance, which makes use of quite a lot of counters to trace accesses to a small variety of rows adjoining to a possible sufferer row. If the entry rely for these aggressor rows reaches a sure threshold, the system points a refresh to the sufferer row. TRR will be integrated throughout the DRAM or within the host CPU.
Nonetheless, this mitigation just isn’t foolproof. For instance, the TRRespass assault confirmed that by concurrently hammering a number of, non-adjacent rows, TRR will be bypassed. Over the previous couple of years, extra refined assaults (Half-Double, Blacksmith) have emerged, introducing extra environment friendly assault patterns.
In response, considered one of our efforts was to collaborate with Jatcexterior researchers, and specialists to outline the PRAC as a brand new mitigation that deterministically detects Rowhammer by monitoring all reminiscence rows.
Nonetheless, present techniques geared up with DDR5 lack help for PRAC or different sturdy mitigations. Because of this, they depend on probabilistic approaches resembling ECC and enhanced TRR to cut back the danger. Whereas these measures have mitigated older assaults, their total effectiveness towards new methods was not absolutely understood till our current findings.
Challenges with Rowhammer Evaluation
Mitigating Rowhammer assaults entails making it tough for an attacker to reliably trigger bit flips from software program. Due to this fact, for an efficient mitigation, we’ve to know how a decided adversary introduces reminiscence accesses that bypass present mitigations. Three key info elements will help with such an evaluation:
How the improved TRR and in-DRAM ECC work.
How reminiscence entry patterns from software program translate into low-level DDR instructions.
(Optionally) How any mitigations (e.g., ECC or TRR) within the host processor work.
Step one is especially difficult and entails reverse-engineering the proprietary in-DRAM TRR mechanism, which varies considerably between completely different producers and system fashions. This course of requires the power to problem exact DDR instructions to DRAM and analyze its responses, which is tough on an off-the-shelf system. Due to this fact, specialised check platforms are important.
The second and third steps contain analyzing the DDR site visitors between the host processor and the DRAM. This may be completed utilizing an off-the-shelf interposer, a software that sits between the processor and DRAM. A vital a part of this evaluation is knowing how a dwell system interprets software-level reminiscence accesses into the DDR protocol.
The third step, which entails analyzing host-side mitigations, is typically non-compulsory. For instance, host-side ECC (Error Correcting Code) is enabled by default on servers, whereas host-side TRR has solely been carried out in some CPUs.
Rowhammer testing platforms
For the primary problem, we partnered with Antmicro to develop two specialised, open-source FPGA-based Rowhammer check platforms. These platforms enable us to conduct in-depth testing on various kinds of DDR5 modules.
DDR5 RDIMM Platform: A brand new DDR5 Tester board to satisfy the {hardware} necessities of Registered DIMM (RDIMM) reminiscence, widespread in server computer systems.
SO-DIMM Platform: A model that helps the usual SO-DIMM pinout appropriate with off-the-shelf DDR5 SO-DIMM reminiscence sticks, widespread in workstations and end-user units.
Antmicro designed and manufactured these open-source platforms and we labored intently with them, and researchers from ETH Zurich, to check the applicability of those platforms for analyzing off-the-shelf reminiscence modules in RDIMM and SO-DIMM kinds.
Antmicro DDR5 RDIMM FPGA check platform in motion.
Phoenix Assaults on DDR5
In collaboration with researchers from ETH, we utilized the brand new Rowhammer check platforms to guage the effectiveness of present in-DRAM DDR5 mitigations. Our findings, detailed within the not too long ago co-authored “Phoenix” analysis paper, reveal that we efficiently developed customized assault patterns able to bypassing enhanced TRR (Goal Row Refresh) protection on DDR5 reminiscence. We had been in a position to create a novel self-correcting refresh synchronization assault method, which allowed us to carry out the first-ever Rowhammer privilege escalation exploit on an ordinary, production-grade desktop system geared up with DDR5 reminiscence. Whereas this experiment was carried out on an off-the-shelf workstation geared up with current AMD Zen processors and SK Hynix DDR5 reminiscence, we proceed to research the applicability of our findings to different {hardware} configurations.
Classes discovered
We confirmed that present mitigations for Rowhammer assaults should not adequate, and the difficulty stays a widespread drawback throughout the trade. They do make it harder “however not inconceivable” to hold out assaults, since an attacker wants an in-depth understanding of the particular reminiscence subsystem structure they want to goal.
Present mitigations primarily based on TRR and ECC depend on probabilistic countermeasures which have inadequate entropy. As soon as an analyst understands how TRR operates, they will craft particular reminiscence entry patterns to bypass it. Moreover, present ECC schemes weren’t designed as a safety measure and are due to this fact incapable of reliably detecting errors.
Reminiscence encryption is an alternate countermeasure for Rowhammer. Nonetheless, our present evaluation is that with out cryptographic integrity, it gives no precious protection towards Rowhammer. Extra analysis is required to develop viable, sensible encryption and integrity options.
Path ahead
Google has been a pacesetter in JEDEC standardization efforts, for example with PRACa completely accepted normal to be supported in upcoming variations of Dr5/LPDDR6. It really works by precisely counting the variety of instances a DRAM wordline is activated and alerts the system if an extreme variety of activations is detected. This shut coordination between the DRAM and the system offers PRAC a dependable option to deal with Rowhammer.
Within the meantime, we proceed to guage and enhance different countermeasures to make sure our workloads are resilient towards Rowhammer. We collaborate with our educational and trade companions to enhance evaluation methods and check platforms, and to share our findings with the broader ecosystem.
Need to be taught extra?
“Phoenix: Rowhammer Assaults on DDR5 with Self-Correcting Synchronization” will probably be introduced at IEEE Safety & Privateness 2026 in San Francisco, CA (MAY 18-21, 2026).
